Quartus_cdb (17.1/18.0) crashes while generating VQM for StratixV for a simple adder

Hi All,

I am using Quartus17.1 as well as Quartus 18.0

quartus_cdb crashes with following error only when StratixV family is used:

*** Fatal Error: Segment Violation at (nil)

Module: quartus_cdb

Stack Trace:

0xbbd90: DEV_DEVICE::get_pad_info() const (ddb_dev)

End-trace

The verilog file, Add_24Ux24U_24U_4.v :# ##########################

module Add_24Ux24U_24U_4 (

in2,

in1,

out1

);

input [23:0] in2,

in1;

output [23:0] out1;

wire [23:0] asc001;

assign asc001 =

+(in2)

+(in1);

assign out1 = asc001;

endmodule# ########################

The tcl file (syn.tcl):# ########################

load_package flow

load_package report

load_package sdc

set module "Add_24Ux24U_24U_4"

proc syn { module family verilogInput} {

set proj [project_new -overwrite $module]

set_global_assignment -name FAMILY $family

set_global_assignment -name DEVICE Auto

set_global_assignment -name VERILOG_FILE ${module}.v

set_global_assignment -name NUM_PARALLEL_PROCESSORS 2

set_instance_assignment -name VIRTUAL_PIN ON -to in*

set_instance_assignment -name VIRTUAL_PIN ON -to in*

set_instance_assignment -name VIRTUAL_PIN ON -to out*

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

execute_module -tool map

execute_module -tool fit

execute_module -tool cdb -args "--vqm=${module}.vqm"

project_close

}

syn $module "StratixV" $module# ########################

Command used to run

> quartus_sta -t syn.tcl

Please let me know any solution to this issue.

Thanks,

Srinivasa