New ContributorHi everybody,
I have a big circuit A that calls sub circuit B twice in its design. Let say sub circuit B is developed, compiled, placed and routed by another person. In A, I want to have 2 design partitions that have exactly the same post-fit placement and route that the other person gave me. Is there anyway to do that in Quartus?
Thank you so much!
Super ContributorYes. If you are using the Pro edition, you can use the design block reuse flow. If you are using the Standard edition, you can do something similar with incremental compilation. See the block-based design user guide here: https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html
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New ContributorHi sstrell,
I am using the standard edition. I have been trying to use the incremental compilation but it it did not work. I exported the post-fit partition for sub circuit B. When I tried to import it to two different partitions in circuit A, it failed because the post-fit net-list preserves all the placement info including where to place each logic of B. Then two different partitions of B in circuit A will share the same location and I can not change it, which cause conflict. Do you have any idea on how to work around this?
Thank you so much!
Super ContributorIf you want to use B in multiple locations, you have to export it using the post-synthesis netlist, not post-fit. Otherwise you have the problem you mention.
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New ContributorSo there is no way to use B in multiple locations while keeping the placement and routing relatively the same, which mean the only difference is location to put B? It more like I want to "copy" B and "paste" it to a different location. Will the Pro edition allow me to do this?
Thank you so much!
Super ContributorEven in Pro you can't do this exactly. You can't "paste" a copy to a different location and expect the resources in that second location to exactly match the original location. That's why you have to rely on the Fitter to place & route the post-synthesis version of the design in the destination project (we call it the "Consumer" project) into resources available at a different location (a forced location with Logic Lock or not).
If your concern is that this is a timing-critical block that you need multiple copies of, you may want to create specific SDC timing constraints for the block that get included with the sub-design. In the Pro edition, timing constraints can automatically be included with the exported .qdb file. In Standard, you'd have to manually recreate these constraints in the destination project.
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Super ContributorWhat we would suggest is to use floor plan, you can refer to
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-compiler.pdf
page 109.
Also, depending on what you want to achieve. what are the purposes that you want to lock down the placement of your design?
Super ContributorAny update?
