Honored Contributor
Honored ContributorThe final answer from Altera on my SR has been this:
--- Quote Start --- Following from your SR last time, this is the update of the handbook that explains the error that you received in this SR. Please refer to Cyclone III I/O chapter handbook, http://www.altera.com/literature/hb/cyc3/cyc3_ciii51007.pdf, DCLK Pad Placement Guidelines, page 7-30, to see the restriction in the QII. --- Quote End --- The said paragraph tells: --- Quote Start --- DCLK Pad Placement Guidelines There is a restriction on the proximity of selected I/O standard inputs and outputs to the DCLK pin on QFP packages. The restriction is to minimize noise coupling from neighboring I/O to the DCLK pin, and is as follows: If an I/O is using 3.0 or 3.3 V I/O standards, there must be one pad of separation between the I/O and the DCLK for the QFP packages. The Quartus II software checks for this restriction. --- Quote End --- There may or may be not plausible reasons to guard DCLK in the said way. That's hard for me to decide. The annoying point is, that an obviously unapplicable I/O standard is assigned to the pin, another, that it took three months until the issue could be clarified in the said way. In the beginning, there hasn't been a qualified error message at all. But I see, that Quartus development is a very complex process. If you intend to include a SFL instance or another function, that accesses the serial flash at runtime, to your design and can't meet the DCLK distance rule, you can try this: - Use a virtual I/O voltage of 2.5V with bank 1 - Assign a different configuration scheme than AS in device options (e.g. PS), cause AS is only allowed with VCCIO of 3.3V (in contrast to the DCLK I/O standard!). The solution worked with original Quartus V7.2, I didn't check it with 7.2SPs or V8. There may be changes that affect the behaviout in this point.
