Quartus 9.1 PCIe pinout fiasco..

Anyone else get bit by this?

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Quartus II Mapping Issue with PCI Express (PCIe) Interfaces Using the

Hard IP Block

The Quartus II software versions 9.1, 9.1 SP1, and 9.1 SP2 incorrectly allow logical

channel 0 to be placed in any physical channel for ×1 and ×4 PCIe Gen1 interfaces

with the hard IP block. For correct operation with the hard IP block, logical channel 0

must be placed in physical channel 0.

This issue is fixed in the Quartus II software version 10.0; however, Altera

recommends upgrading to the Quartus II software version 10.0 SP1. If you have

already designed or fabricated your boards using the incorrect mapping, file a service

request using mysupport.altera.com for assistance to remedy this problem

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My board is built and assembled already.

I spent the last two weeks trying to figure out why my PCIe express core wouldn't work till I found this in the errata. When I compile it under 10.x it now errors out on the pins I chose for PCIe.

Yes, I've logged this with Altera support. The response was effectively "I don't see a problem, your design compiles fine in Quartus 9.1".. Sigh...

If anyone has received a coherent support response on this issue, please share it.

I'm hoping I can use the soft PCIe core to work around this. Bet I have to pay for it.