Altera_Forum
Honored Contributor
15 years agoQuartus 9.1 EPCS flashing problem! rev A
I have created an SOPC system, using Quartus 9.1 (no SPx installed after reading the problems introduced by these service packs) on a custom board with an EP1C12 Cyclone device and EPCS4 device with the following components:
1. NIOS 2 processor (configured with a JTAG Debug Level 1) 2. EPCS Controller 3. On-Chip RAM 4. Sysid 5. JTAG 6. 2 each UART After I have compiled the design, I have created a small application which receives characters from one of the serial interface and it replicates them to the JTAG port and to the UART port from which the data have been received. I have compiled, linked and run the application under the “Run As hardware” using the Eclipse IDE configuration and everything is working fine. The problems have begin when I have tried to flash the EPCS; indeed, even if the entire flash process completes without any error and after resetting the system, I can verify that the application is running correctly, when I perform a power up, the FPGA is no longer configured correctly or the application is not uploaded. To troubleshoot this problem I have taken the following steps: 1. Created the same project with the same characteristics and using the same software files under Quartus 8.0 (again no SP installed); 2. Verified the configuration and the software functionality by testing the system with the “Run As… Hardware” 3. Flashed the EPCS successfully and verified that everything boots correctly The above steps prove that the there are no issues associated with the hardware and my custom board; interesting enough, I have notice that under Quartus 8.0 the total current consumption is in the order of 95mA, while when the FPGA is running with the configuration generated under Quartus 9.1 it increases to 130mA. I assume this change of current is caused by a quite different configuration file for the FPGA despite the 2 designs under the 2 different Quartus version are identical (in terms of components instantiated and pin out utilization). Following some of the indication taken from the Altera Forum, I have also tried to perform the conversion of the .SOF and .ELF files generated by the Quartus 9.1 and programming the EPCS using the Quartus 8.0 tools and flash programmer, but with the same results. Is there any indication on to get down to the bottom of this problem? I am of the impression that something is not correct with how the .SOF file is generated by the assembler under the 9.1 version. Just as a confirmation to all of the above, I have spent time to recreate the same project also using Quartus 10 (and what I mean, not importing the project, but creating it again from scratch) and I have been able to successfully program the FPGA. If someone of You will ask, then why I do not use Quartus 10, the simple answer is that it does not provides the Waveform Editor which I use to generate my testbenches to verify the design with ModelSIM-Altera. Any help is seriously appreciated; thanks in advance