quartus 7.2 cannot launch the modelsim-altera 6.1g

hi: guys

i use the quartus 7.2 web edition and modelsim altera6.1g to simulate next program

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity fpdiv is

port (

DIVz: out STD_LOGIC;

A: in STD_LOGIC_VECTOR (7 downto 0):="11111111";

B: in STD_LOGIC_VECTOR (7 downto 0):="00000010";

data_out: out STD_LOGIC_VECTOR (7 downto 0)

);

end fpdiv;

architecture fpdiv_arch of fpdiv is

signal REMAINDERS0 : STD_LOGIC_VECTOR (5 downto 0);

signal REMAINDERS1 : STD_LOGIC_VECTOR (5 downto 0);

signal REMAINDERS2 : STD_LOGIC_VECTOR (5 downto 0);

signal REMAINDERS3 : STD_LOGIC_VECTOR (5 downto 0);

signal DIVISORS0 : STD_LOGIC_VECTOR (5 downto 0);

signal DIVISORS1 : STD_LOGIC_VECTOR (5 downto 0);

signal DIVISORS2 : STD_LOGIC_VECTOR (5 downto 0);

signal DIVISORS3 : STD_LOGIC_VECTOR (5 downto 0);

signal Q_TEMP : STD_LOGIC_VECTOR (7 downto 0);

signal Z0 : STD_LOGIC_VECTOR (2 downto 0);

signal Z1 : STD_LOGIC_VECTOR (2 downto 0);

signal ZERO : STD_LOGIC;

begin

Z0 <= (others => '0');

Z1 <= (others => '0');

DIVISORS0 <= Z0 & B(2 downto 0);

REMAINDERS3 <= Z1 & A(2 downto 0);

DIVISORS1 <= DIVISORS0(4 downto 0) & '0';

DIVISORS2 <= DIVISORS1(4 downto 0) & '0';

DIVISORS3 <= DIVISORS2(4 downto 0) & '0';

Q_TEMP(0) <= '1' when (REMAINDERS1 >= DIVISORS0) else '0';

Q_TEMP(1) <= '1' when (REMAINDERS2 >= DIVISORS1) else '0';

Q_TEMP(2) <= '1' when (REMAINDERS3 >= DIVISORS2) else '0';

Q_TEMP(3) <= '1' when (REMAINDERS1 >= DIVISORS0) else '0';

Q_TEMP(4) <= '1' when (REMAINDERS2 >= DIVISORS1) else '0';

Q_TEMP(5) <= '1' when (REMAINDERS3 >= DIVISORS2) else '0';

Q_TEMP(6) <= '1' when (REMAINDERS2 >= DIVISORS1) else '0';

Q_TEMP(7) <= A(7) xor B(7);

REMAINDERS2 <= REMAINDERS3 - DIVISORS2 when Q_TEMP(2) = '1' else REMAINDERS3;

REMAINDERS1 <= REMAINDERS2 - DIVISORS1 when Q_TEMP(1) = '1' else REMAINDERS2;

REMAINDERS0 <= REMAINDERS1 - DIVISORS0 when Q_TEMP(0) = '1' else REMAINDERS1;

ZERO <= '1' when B(6 downto 0) = Z1 else '0';

DIVz <= '1' when ZERO = '1' else '0';

data_out <= (others => '0') when ZERO = '1' else Q_TEMP;

end fpdiv_arch;

the compile is success , when i use modelsim-altera to run EDA RTL simualtion i get next problem.

Info: Quartus(args): --rtl_sim fpdiv fpdiv

Info: Start Nativelink Simulation process

Info: NativeLink has detected VHDL design -- VHDL simulation models will be used

Info: Starting NativeLink simulation with ModelSim-Altera software

Error: Can't launch the ModelSim-Altera software -- the path to the location of the executables for the ModelSim-Altera software were not specified or the executables were not found at specified path.

Error: You can specify the path in the EDA Tool Options page of the Options dialog box or using the Tcl command set_user_option.

Error: NativeLink simulation flow was NOT successful

Info: For messages from NativeLink scripts, check the file C:/altera/72/quartus/fpdiv_nativelink_simulation.rpt

i already installation modelsim-altera and run is ok.

i set the setting in quartus 7.2 is following,the test bench is generation from quartus

testbench name: fpdiv.vht

top level model in test bench : fpdiv_vhd_tst

design instance name in test bench :TB

i set the path in environment variance point to the modelsim-altera

why i have this problem please tell me , i am a new coming.

thanks