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rva1311's avatar
rva1311
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3 years ago

Quartus 22 - University Program VWF - Ouputs stays to an undefined state

Hi, I try to use Quartus 22.1 on Linux for the target 5CSEBA6U23I7. Simulations work when I use Tool > Run Simulation Tool > RTL Simulation. But when I want to simulate a University Program ...
sstrell's avatar
sstrell
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3 years ago

Without seeing the design, there's no way to know what's going on here. Can you provide the code?

  • rva1311's avatar
    rva1311
    Icon for New Contributor rankNew Contributor
    3 years ago

    Here the used code.

    library ieee;

use ieee.std_logic_1164.all;

entity pmu is
	port(
		clk : in std_logic;
		rst : out std_logic
	);
end pmu;

architecture rtl of pmu is

begin

	rst <= not clk; 

end rtl;

    Thank you for your help.