Quartus 21.1: Error (10170): Verilog HDL syntax error at ... near text: "import"; expecting ";".

I dowload the related imported package using this in the .qsf:

set_global_assignment -name SYSTEMVERILOG_FILE -lib ethosu55_lib ${data}/ip_arm_lib/ip_hactar_256/ethosu55/logical/ethosu55/verilog/ethosu55_pkg.sv

set_global_assignment -name SYSTEMVERILOG_FILE -lib ethosu55_lib ${data}/ip_arm_lib/ip_hactar_256/ethosu55/logical/ethosu55_mac/verilog/ethosu55_mac_pkg.sv

And the RTL itself that contains the import (later in the qsf, not before the two previous files):

set_global_assignment -name SYSTEMVERILOG_FILE -lib ethosu55_lib ${data}/ip_arm_lib/ip_hactar_256/ethosu55/logical/ethosu55_sb/verilog/ethosu55_sb.sv

The header file mention this:

//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------

I've never used this, but it looks like the import commands need to be inside your module (after the port list and semicolon), not in the module declaration, or completely outside the module.

https://blogs.sw.siemens.com/verificationhorizons/2020/07/15/what-does-importing-a-systemverilog-package-mean/

https://verilogguide.readthedocs.io/en/latest/verilog/package.html