Quartus 20.1.0 Synthesis of System Verilog Interfaces

Hi @bitstreamer

You mentioned that the Quartus does not synthesize interface logic consistently, may I further understand the issue behind?

I found that Quartus has interface template that you can use, perhaps you can try to synthesis using the Interface template provided, to check if the issue still persists?

1. In the new .sv file created, Right-click and scroll to Insert template

2. A window will pop up. Click SystemVerilog > Design Units > Interfaces

Interface Declaration Template:

interface <interface_name>(<port_list>);

	// Variable Declaration(s)
	// Modport Declaration(s)
	// Function/Task Declaration(s)
	// Always Construct(s)
	// Generate(s)
	// An interface cannot instantiate a module but it may
	// instantiate an interface

endinterface

Modport Declaration Template:

// A modport limits the access to the objects in an interface.  Each port
// must correspond to an object in the enclosing interface.  
modport <modport_name>(<port_list>);

// Examples
modport slave(input clk, input sel, output byte data);
modport master(input clk, output sel, input byte data);

Fyi, we have a team of people working on Intel Forum, and I believe you will most likely find me or my colleagues, on questions related to Quartus tool. Perhaps you may help to share us your feedback regarding to the forum support for the past few years?

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.