ContributionsMost RecentMost LikesSolutionsArria 10 JESD DLL FIFO error the receive status register is showing that the DLL FIFO is empty. The receive PMA is locked to data on all lanes. The only issue being reported is the DLL FIFO being empty. The clocks are correct on both the link side and the reference clock. I am assuming the DLL FIFO has some clock multiplexer that isn't being set correctly, or something is disabled between the PMA and PCS, or somehow the comma detection circuit is disconnected from the JESD core. There is no description of a DLL FIFO, and there is no diagram. What are all the possible sources of why the DLL FIFO would be empty? Re: Quartus Prime Standard Edition "Remove IP Component from Project" Greyed out Yes - I tried to create a new project, but it allows removal of the IP. What could possibly cause a IP component to not have the capability to be removed? I'd assume this would go beyond file permissions. Re: What is clklow signal of fPLL That's a direct quote from the user guide, but I don't think this answers the question. Where is the external soft lock detection described? Google doesn't show any reference for an Intel soft lock circuit. Re: PreSICE Avalon calibration Just debugging the ATX for a transceiver application. Yes, working within powerdown to reconfigure - trying to achieve lock - I am assuming lock will assert while in powerdown - but I don't see a spec for it. I also don't see timing requirements for the minimum amount of time needed from the lock assertion to when the transceivers resets should be de-asserted. I was thinking 10 microseconds to be safe. Thank you for the link. Look forward to your thoughts. Re: PreSICE Avalon calibration 1. Not fPLL - ATX. 2. Good to know - but it's definitely not working with those two dependencies. Eval board from Intel. It just doesn't lock. Any suggestions? Re: Quartus Prime Standard Edition "Remove IP Component from Project" Greyed out Unfortunately can't. I'll try and create a similar project. PreSICE Avalon calibration In the user guide ug_arria10_xcvr_phy, section 7.5 there is a recalibration example. Does this work for PLLs that are not connected to transceivers, or is being connected to a transceiver a requirement for PreSICE? The PLL does not assert lock on an eval board, but does lock when connected to a transceiver. When not connected to a transceiver, the pll_powerdown pin is controlled via a register. When I complete step 3, writing a one to enable calibration - the register clears on write. Is this supposed to happen? Re: Quartus Prime Standard Edition "Remove IP Component from Project" Greyed out Re: Quartus Prime Standard Edition "Remove IP Component from Project" Greyed out You can create a design in platform designer and add it within the design hierarchy at a later time. i'll post one tomorrow, thank you for your consideration! Re: Quartus Prime Standard Edition "Remove IP Component from Project" Greyed out It happens regardless if the IP is instantiated or not. Seems to apply to all IP - I've never seen it not greyed out.