bitstreamer
Occasional ContributorJoined 6 years ago
User Profile
Occasional Contributor
User Widgets
Contributions
Arria 10 JESD DLL FIFO error
the receive status register is showing that the DLL FIFO is empty. The receive PMA is locked to data on all lanes. The only issue being reported is the DLL FIFO being empty. The clocks are correct on both the link side and the reference clock. I am assuming the DLL FIFO has some clock multiplexer that isn't being set correctly, or something is disabled between the PMA and PCS, or somehow the comma detection circuit is disconnected from the JESD core. There is no description of a DLL FIFO, and there is no diagram. What are all the possible sources of why the DLL FIFO would be empty?Re: PreSICE Avalon calibration
Just debugging the ATX for a transceiver application. Yes, working within powerdown to reconfigure - trying to achieve lock - I am assuming lock will assert while in powerdown - but I don't see a spec for it. I also don't see timing requirements for the minimum amount of time needed from the lock assertion to when the transceivers resets should be de-asserted. I was thinking 10 microseconds to be safe. Thank you for the link. Look forward to your thoughts.PreSICE Avalon calibration
In the user guide ug_arria10_xcvr_phy, section 7.5 there is a recalibration example. Does this work for PLLs that are not connected to transceivers, or is being connected to a transceiver a requirement for PreSICE? The PLL does not assert lock on an eval board, but does lock when connected to a transceiver. When not connected to a transceiver, the pll_powerdown pin is controlled via a register. When I complete step 3, writing a one to enable calibration - the register clears on write. Is this supposed to happen?
