Quartus 20.1.0 Synthesis of System Verilog Interfaces

Hi @bitstreamer

I am not familiar with modports but you may checkout the IEEE Standard for SystemVerilog (Section 25.5 Modports) document for code example.

Or you may checkout the webpage below on how to code it.

https://www.chipverify.com/systemverilog/systemverilog-modport

May I know which documents that you refer to previously, that stated the system verilog capabilities for Quartus17.0?

You may checkout the webpage below for further information on SystemVerilog Synthesis Support in Intel Quartus Prime Software.

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_list_sys_vlog.htm

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.