MichaelB
Occasional Contributor
Occasional ContributorQuartus 19.2 issue placing IO PLL clock pins for HBM2
Hi,
I'd like to place the reference clock pins for the IO PLL for both HBM2s available on Stratix 10 1SM16BEU2F55E2VG.
I have assigned the reference clock for top HBM2 to PIN_BA35 and for bottom ...
Hi Michael
BA35 and U35 is reference clock for eSRAM. Please check the pin out file for the UIB_PLL_REF_CLK pin locaton for HBM2 pll_ref_clk
Here is the pin placement guideline for HBM2 pll_ref_clk pin
Place this reference clock input on the
UIB_PLL_REF_CLK_00 pins while using
the HBM2 device on the bottom of the
FPGA, or the UIB_PLL_REF_CLK_01
pins while using the HBM2 on the top
of the FPGA.
