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qrive1's avatar
qrive1
Icon for New Contributor rankNew Contributor
6 years ago

Quartus : Master clock could not be derived

I am working on Stratix 10 and Quartus 18.1 pro. Im using a PLL created with the IP 'IOPLL' in order to create a 40MHz clock from a 320MHz clock input from Si5341 ("pll_40"). Normally, I don't ha...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

sorry , caught into other stuff and missed out ,

Actually i am not sure why not for the both the clock, I will raise the quires to the internal team and come back to you .

Meanwhile if you find anything similar can you let me know as well so i can learn from you.

Thank you ,

Regards,

Sree