Quartus - Asynchronous RAM

Question

Hi!!!!

Is it possible to implement asynchronous RAM in VHDL for the Stratix II device?

If it is possible, how can I do?

I need your help... is very important for me because ,I'm working with this device in my final career proyect...

Thx for your help!!!

Mary

altera_forum · Answer

I'm working with the megafunction altsyncram,  Should I change some parameters to the memory that is generated?

altera_forum · Answer

Also,how I must work with the Pseudo-Asynchronous Modes??? Thx for your help!!!!

altera_forum · Answer

hi  i need an asynchronous RAM ?  i cant find one with no clk port!  plz help me  thanks in advance.

altera_forum · Answer

What FPGA are you targetting? Most current FPGA only have synchronous RAMs.

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