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You could simulate the qsys system using the altera bus functional model? It can also help to create a test bench for the vhdl to check its doing what you expect.
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Hi, the VHDL is already proven out as a qsys component as it has been used in an earlier version and with cyclone III and IV devices, this has been in use for a number of years. Unfortunately we now need to move to a MAX 10 device, whcih means using quartus 14 and later, which is where the problem seems to creep in.
However, it looks as though this problem is not unique to my IP. If i download the Avalon MM Slave Template and use that IP it appears that I have the same problem, what is interesting is that normally the new qsys versions (14+) all complain about having multiple signal types of the same name within a conduit. However the MM Slave template tcl file that is generated has export for every signal in the conduit and qsys does not complain.
Still not working, and its getting more frustrating!
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