Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi all,
I changed the address locations to the expected address location by hand (in the given file above, the "<project name>_mm_interconnect_2_router.sv") and now it seems to work fine. So I think this is a bug in Qsys, or could it also be a settings thing? Anyhow, the code snippet above now becomes:// -------------------------------------------------------
// Figure out the number of bits to mask off for each slave span
// during address decoding
// -------------------------------------------------------
localparam PAD0 = log2ceil(64'h08 - 64'h0);
localparam PAD1 = log2ceil(64'h28 - 64'h20);
localparam PAD2 = log2ceil(64'h48 - 64'h40);
localparam PAD3 = log2ceil(64'h68 - 64'h60);
// -------------------------------------------------------
// Work out which address bits are significant based on the
// address range of the slaves. If the required width is too
// large or too small, we use the address field width instead.
// -------------------------------------------------------
localparam ADDR_RANGE = 64'h68;
localparam RANGE_ADDR_WIDTH = log2ceil(ADDR_RANGE);
localparam OPTIMIZED_ADDR_H = (RANGE_ADDR_WIDTH > PKT_ADDR_W) ||
(RANGE_ADDR_WIDTH == 0) ?
PKT_ADDR_H :
PKT_ADDR_L + RANGE_ADDR_WIDTH - 1;
localparam RG = RANGE_ADDR_WIDTH-1;
localparam REAL_ADDRESS_RANGE = OPTIMIZED_ADDR_H - PKT_ADDR_L;
reg address;
always @* begin
address = {PKT_ADDR_W{1'b0}};
address = sink_data;
end
// -------------------------------------------------------
// Pass almost everything through, untouched
// -------------------------------------------------------
assign sink_ready = src_ready;
assign src_valid = sink_valid;
assign src_startofpacket = sink_startofpacket;
assign src_endofpacket = sink_endofpacket;
wire default_destid;
wire default_src_channel;
// -------------------------------------------------------
// Write and read transaction signals
// -------------------------------------------------------
wire read_transaction;
assign read_transaction = sink_data;
soc_system_mm_interconnect_2_router_default_decode the_default_decode(
.default_destination_id (default_destid),
.default_wr_channel (),
.default_rd_channel (),
.default_src_channel (default_src_channel)
);
always @* begin
src_data = sink_data;
src_channel = default_src_channel;
src_data = default_destid;
// --------------------------------------------------
// Address Decoder
// Sets the channel and destination ID based on the address
// --------------------------------------------------
// ( 0x0 .. 0x400000000 )
if ( {address,{PAD0{1'b0}}} == 35'h0 && read_transaction ) begin
src_channel = 4'b1000;
src_data = 3;
end
// ( 0x20 .. 0x400000020 )
// ( no optimization for non-address-span aligned address range )
if ( ( ( sink_data >= 'h20) && (sink_data < 'h28) )
&& read_transaction ) begin
src_channel = 4'b0010;
src_data = 2;
src_data = sink_data - 'h20;
end
// ( 0x40 .. 0x400000040 )
// ( no optimization for non-address-span aligned address range )
if ( ( ( sink_data >= 'h40) && (sink_data < 'h48) )
&& read_transaction ) begin
src_channel = 4'b0100;
src_data = 1;
src_data = sink_data - 'h40;
end
// ( 0x60 .. 0x400000060 )
// ( no optimization for non-address-span aligned address range )
if ( ( ( sink_data >= 'h60) && (sink_data < 'h68) )
&& read_transaction ) begin
src_channel = 4'b0001;
src_data = 0;
src_data = sink_data - 'h60;
end Hope this helps others with this problem. However I am still very interested in the reason of this problem. Therefore if you could provide me (a part of) the clue, it would be very welcome!