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Altera_Forum
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9 years ago

Qsys testbench: component not bound

Hello, I'm facing a problem with my Qsys generated testbench. I generated a VHDL testbench from Qsys. In Qsys I used three own components and one clock input, all connected using Avalon Streami...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

That makes sense. The TCL file can't be created with the top level because the test bench doesn't exist if you didn't tell the tool to create one when building the component.