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Altera_Forum
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9 years ago

Qsys testbench: component not bound

Hello, I'm facing a problem with my Qsys generated testbench. I generated a VHDL testbench from Qsys. In Qsys I used three own components and one clock input, all connected using Avalon Streami...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thank you, you are correct. The TCL file for the components in Qsys were missing the definition of the top level entity for the simulation file set (why can I set the top level entity for synthese in Qsys and for simulation not?). I fixed this and now ModelSim runs the simulation.