Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorQsys testbench: component not bound
Hello, I'm facing a problem with my Qsys generated testbench. I generated a VHDL testbench from Qsys. In Qsys I used three own components and one clock input, all connected using Avalon Streami...
Altera_ForumHonored Contributor
Honored ContributorHave you told modelsim that the test bench is the top level entity? Also, does you test bench instantiate your design and map the ports to your test bench?
