Qsys submodule entities unbound to top module

Hi,

I found this problem trying to simulate in Questasim from a Qsys generated system. Specifically the 3-Wire SPI IP does not appear to bound to the top level .vhd file. The design will compile, but is left unbound when trying to simulate.

Here is the QuestaSim error:

# ** Warning: (vsim-3473) Component instance "ad5734r : AARDVARK_SPI_AD5734R" is not bound.#     Time: 0 ps  Iteration: 0  Instance: /aardvark_spi_tb/uut File: ./../AARDVARK_SPI.vhd

Here are copies of the Qsys top level entities:

component AARDVARK_SPI_AD5734R is        port (
            clk           : in  std_logic                     := 'X';             -- clk
            reset_n       : in  std_logic                     := 'X';             -- reset_n
            data_from_cpu : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
            data_to_cpu   : out std_logic_vector(31 downto 0);                    -- readdata
            mem_addr      : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- address
            read_n        : in  std_logic                     := 'X';             -- read_n
            spi_select    : in  std_logic                     := 'X';             -- chipselect
            write_n       : in  std_logic                     := 'X';             -- write_n
            irq           : out std_logic;                                        -- irq
            MISO          : in  std_logic                     := 'X';             -- export
            MOSI          : out std_logic;                                        -- export
            SCLK          : out std_logic;                                        -- export
            SS_n          : out std_logic                                         -- export
        );

But the actual submodules for the 3-Wire SPI are not the same:

module AARDVARK_SPI_AD5734R (                              // inputs:
                               MISO,
                               clk,
                               data_from_cpu,
                               mem_addr,
                               read_n,
                               reset_n,
                               spi_select,
                               write_n,
                              // outputs:
                               MOSI,
                               SCLK,
                               SS_n,
                               data_to_cpu,
                               dataavailable,
                               endofpacket,
                               irq,
                               readyfordata
                            )
;
  output           MOSI;
  output           SCLK;
  output           SS_n;
  output   data_to_cpu;
  output           dataavailable;
  output           endofpacket;
  output           irq;
  output           readyfordata;
  input            MISO;
  input            clk;
  input    data_from_cpu;
  input    mem_addr;
  input            read_n;
  input            reset_n;
  input            spi_select;
  input            write_n;

Anyone have any experience with this? Know any "minimally invasive" work around so I can still use my test bench in Questasim?

Thanks