QSYS simulation error when using VHDL testbench simulation model

Hi,

I'm running a simulation on a simple QSYS system.

The QSYS system is the same as the one used in the AN351 application "Simulating Nios II Embedded Processor Designs", having a clock source, Nios II Processor, On-chip RAM and JTAG UART.

The "Create testbench Qsysy system" is set to: Simple, BFMs for clocks and resets".

The "Hello World" SW application is created in Eclipse SBT and used as stimulus for the QSYS system.

As long as I select Verilog for the "Create testbench simulation model", the simulation runs as it should, the JTAG UART prints out "Hello World" to the console durring the simulation.

If I change the "Create testbench simulation model" to VHDL, generate and try to run the simulation, I'm getting the following error message:

# -- Compiling entity niosii_system_nios2_instruction_master_translator_avalon_universal_master_0_agent# ** Error: (vcom-7) Failed to open library file "C:\an351_design\software\hello_world_an351\obj\default\runtime\sim\mentor\libraries\niosii_system_tb_nios2_instruction_master_translator_avalon_universal_master_0_agent/niosii_system_nios2_instruction_master_translator_avalon_universal_master_0_agent" in read/write/execute mode.# No such file or directory. (errno = ENOENT)# ** Error: C:/an351_design/niosii_system/testbench/niosii_system_tb/simulation/submodules/niosii_system_nios2_instruction_master_translator_avalon_universal_master_0_agent.vho(58): VHDL Compiler exiting# C:/altera/11.1/modelsim_ase/win32aloem/vcom failed.

I tried following the path inorder to locate the "niosii_system_nios2_instruction_master_translator_avalon_universal_master_0_agent" file, but I could not find it

Does anyone know whats going on here?

Saber890