Qsys-Problem with read latency of registered inputs in tri-state bridge

Hi

I switched from SOPC builer to Qsys (Quartus 11.0sp1) today.

On my custom board I have a CFI flash device (S29GL128P10FF010) connected to my SOPC system through a tristate bridge. A DSP device (ADSP-21371) is connected to the flash through a custom designed tri-state bridge master.

At startup, the DSP boots from the flash with a pre-defined access time of 250ns (slowest possible). My FPGA (Cyclone III) is running at 30MHz and uses 6 clock cycles (50ns read wait, 85ns setup, 25ns hold + 1clock cycle = 200ns) to fetch the data from the flash device.

This was only possible by setting the incomming signals to not registered in the SOPC tri-state bridge. As far as I understand, all signals are now registered with Qsys new tri-state bridge concept and there is no way to change this.

However, there have been three new parameters integrated in the signal timings of the generic tri-state controller. The automatic converter set them to:

- Maximum pending read transactions = 3

- Turnaround time = 2

- Read latency = 2

I don't know what these parameters exactly do, but now it takes 10 clock cycles (333ns) to receive data from the flash which is too slow for the DSP! :(

=> Why are there 4 additional clock cycles (I would expect 2)?

=> Is there a way to unregister the input signals - or to use the old SOPC tri-state bridge controller with Qsys?

=> Will changing the timing parameters help anything?

=> Is there a detailed description with timing diagrams on these new parameters available somewhere?

I'll be glad for any suggestions.

Best Regards

Simon