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RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
6 years ago

Qsys now Platform designer, no error , error at same time, on wrong Avalon parameter.

My IP core design, core was not working and error was hidden, production fabric report component as ok, found debugging memory address was wrong. Added missing byteenable was on conduit by error....
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

May I know which version and edition of the software you are using? Could you provide a test case and steps to reproduce the error?

Thanks

RRomano001's avatar
RRomano001
Icon for Contributor rankContributor
6 years ago

Versionless, both 18.1 and 15.0 where same, I recently removed 16.1 and 17.1.

Avalon bus, wrong Symbol size with byteenable size 2 generate wrong Core.

Error is partially captured on waveform but doesn't block code generation.

Generating an IP assign all signal but byteenable (reread first post)

moving byteenable from wrong interface produced this error.

If you are not able to reproduce I can build two snippet, this is stable regardless of OS or version.