Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Qsys not generating same files in Simulation folder for VHDL vs Verilog?

So I have wondered what is going on here and it seems there is a bug in the program. I am using Altera Quartus II 15.0 64 bit. I select SRAM/SSRAM controller from the IP catalog. Then I click gene...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

when I select VHDL a folder named submodels is not creating in the folder named simulation which means that I cannot carry out simulation. Atleast it should give me a warning message for this but it does not. For 2 full days I was confused what is going on since I am new to Qsys as well.