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Altera_Forum
Honored Contributor
9 years agoQsys Interconnect - force usage of "response" signal
Hi, the Avalon IP Specification refers to the response[1:0] signal as an optional signal. However there is complete silence in the rest of the document how to activate it. In my case I am using...
Altera_Forum
Honored Contributor
9 years agoThat's correct, the response depth dictates how many downstream reads can be in flight. The reason why it's called the response FIFO depth is being read data is technically a response to a read commands.
If you need clock crossing in your system if you rely on Qsys to insert clock crossing adapters in the system then the response information will propagate. I know there are plenty of reasons to use the clock crossing bridge instead of relying on Qsys but I think that's the only valid workaround aside from creating a new clock crossing bridge that supports response signaling.