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Honored Contributor
Honored ContributorQsys-generated .SDC files for HPS generate zillions of warning messages
I have a Qsys design named "soc_system" which instantiates the HPS. This is a Cyclone V SOC, running Quartus Prime 17.0.
When generating HDL, Qsys seems to be outputting two SDC files: soc_system_hps_fpga_interfaces.sdc and soc_system_hps_hps_io_border.sdc. Both these files seem to be automatically included in the project under soc_system.qip. Both of these files generate compile warnings on every single line, thereby resulting in hundreds and hundreds (and hundreds more) spurious warning messages completely clogging my compile reports. Examples: On soc_system_hps_hps_io_border.sdc, the first warnings look like this: Warning (332174): Ignored filter at soc_system_hps_hps_io_border.sdc(1): hps_io_hps_io_emac1_inst_TX_CLK could not be matched with a port Warning (332049): Ignored set_false_path at soc_system_hps_hps_io_border.sdc(1): Argument <to> is an empty collection Info (332050): set_false_path -from * -to [get_ports hps_io_hps_io_emac1_inst_TX_CLK] The rest are similar. The reason is that my top-level ports are not named that way. Those names reflect the names of the ports to the soc_system.v module. On soc_system_hps_fpga_interfaces.sdc, the first warnings looks like this: Warning (332174): Ignored filter at soc_system_hps_fpga_interfaces.sdc(3): *fpga_interfaces|f2sdram~FF_3768 could not be matched with a register Warning (332049): Ignored set_false_path at soc_system_hps_fpga_interfaces.sdc(3): Argument <from> is an empty collection Info (332050): set_false_path -from [get_registers {*fpga_interfaces|f2sdram~FF_3768}] Here I have less insight into the nature of the problem. I am not clear if this is normal, or if it's an indication that there's something wrong in my design or on my project configuration, or what I can do about it. Anyone have any insight?
