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bigcheesefuzz's avatar
bigcheesefuzz
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7 years ago

QSYS export a signal and use as a connection

Hello, I'm trying to debug an FPGA / NIOS design at the moment for an intermittent bug, I'd like to bring a number of internal NIOS signals to pins on my FPGA. However when I set a signal (e.g. ...
VVavr1's avatar
VVavr1
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7 years ago

In the case of debug_reset_request which is Reset Output, you can solve your problem by adding Reset Bridge component to your Platform Design.