Qsys Custom Component Problem

When I set up the custom component, the MM-Slave interface includes the signals

writedata, readdata, address, chipselect, write, and waitrequest_n. It also

has interfaces for the clock and reset. Under the signals tab, the waitrequest_n

signal name was assigned to the MM-slave interface, assigned the waitrequest_n

signaltype, and assigned as an output. When observing the behavior with SignalTap,

waitrequest_n behaves as if it is waitrequest. I've attached a SignalTap trace

of the failing bus cycle. Both the chipselect and write signals are truncated

to a single clock cycle.

If I rebuild the design after modifying the top level hdl by inverting the

waitrequest_n signal from the instantiation of the new core before sending it

back to the Qsys system instantiation, then the bus cycle works correctly. In

that configuration, both chipselect and write signals have a duration of two

clock cycles as expected since the new core deasserts waitrequest_n (high) at

the begining of the second clock cycle.

During this process, I have been working with my distributor's FAE. He was able

to reproduce the same incorrect behavior on the waitrequest_n signal using a

completely different experimental design than I have. After that, I submitted a

Service Request to Altera and am awaiting their response.