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Altera_Forum
Honored Contributor
8 years agoThis helped me a lot, thank you!
I had one more step to get it to stop with the "null" thing even after fixing the syntax errors: My source file has some System Verilog in it, so I renamed it from myfile.v to myfile.sv and then it finally accepted it. BitBuster's comment above on VHDL version twigged this idea for me. (I'm using Quartus 14.1 for the record).