Forum Discussion
Altera_Forum
Honored Contributor
9 years agoProblem solved for me. I had a typo in the vhdl source file.
I suspect that it can also be affected by what language version of VHDL you are using. (-87, -93, -2002 or -2008) Found this: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05312011_49.html