Qsys Component Editor for Custom Logic

So I actually figured out what was wrong... kind of. I didn't realize you needed a top level file to kind of interface between the actual file and qSys. Seems a bit strange since it was able to populate the list of signals but whatever. I now have definitely working conduits, however I guess my avalon MM implementation is off. This is my actual code I've been using to try to figure out what is going wrong. Top level included for completeness' sake.

I'm not trying to blow off your simulation comments (again) but this seems to be a protocol implementation? Manythanks

Notes:

This is being used to try to talk to RAM initialized with data in it from a .hex

Code gets hung up waiting for WaitRequest

enable is connected to a debounced PB active high. LEDs are active low

Logic:

module ReadRAM(clk,reset,waitR,readData,read,addr,BE,enable,led1,led2,led3);
//Avalon Signals
input clk,reset,waitR;
input  readData;
output reg read = 0;
output reg  BE = 'b1111;
output reg addr = 'h00000000;
//Peripheral Signals
input enable
output reg led1 = 1;
output reg led2 = 1;
output reg led3 = 1;
integer caseMaster = 0;
reg  data = 'h00000000;
always @(posedge clk) begin
	case(caseMaster)
		0: begin	//check enable
			if(enable==1) begin
				caseMaster = 1;
			end
		end
		1: begin	//set up registers & go
			addr = 'h00000000;
			read = 1;
			led1 = 0;
			caseMaster = 2;	
		end
		2: begin	//wait for RAM to be ready and pull data
			if (waitR == 0 begin)
				led2 = 0;
				data = readData;
				read = 0;
				caseMaster = 3;
			end
		end
		3: begin	//if data is good, ping led3.  Reset caseMaster
			if (data != 'h00000000) begin
				led3 = 0;
			end
			if (enable == 0) begin
				caseMaster = 0;
			end
		end
	endCase
end
endmodule

What seems to be happening is waitRequest stays high and never comes back down, which means it is never indicating it is ready. This seems to me that it could only be a result that the read request isn't getting there, but I don't understand how that is the case if it is mapped appropriately in the component editor.

Top level connecty file

module readRAMInt(clock,reset,waitRequest,readData,
	read,address,byEn,
	enable,led1,led2,led3);
	input clock,reset,waitRequest;
	input  readData;
	output read;
	output  byEn;
	output  address;
	input enable;
	output led1,led2,led3;
	wire wClock, wReset,wWaitRequest;
	wire  wReadData;
	wire wRead;
	wire  wAddress;
	wire  wByEn;
	wire wEnable;
	wire wLed1,wLed2,wLed3;
	ReadRAM u1(.clk(wClock),.reset(wReset),.waitR(wWaitRequest),
		.readData(wReadData),.read(wRead),.addr(wAddress),.BE(wByEn),
		.enable(wEnable),.led1(wLed1),.led2(wLed2),.led3(wLed3);
	//Avalon Inputs
	assign wClock = clock;
	assign wReset = reset;
	assign wWaitRequest = waitRequest;
	assign wReadData = readData;
	//Avalon Outputs
	assign read = wRead;
	assign address = wAddress;
	assign byEn = wByEn;
	//User Inputs
	assign wEnable = enable;
	//User Outputs
	assign led1 = wLed1;
	assign led2 = wLed2;
	assign led3 = wLed3;
endmodule