Qsys Component Editor for Custom Logic

So thank you all for the notes on simulation. I'll look at that but I would like to explain in very long winded fashion where I'm at on the actual problem:

To debug this blasted thing I made 2 attempts at further understanding the problem. First I have a debounced button that goes into qsys via a conduit in my custom component. Within in always at posedge clk begin statement the first line says if the button == 1 (it is active high) then change an output reg to 1 which then goes to an LED (I haven't figured out how to probe stuff directly on a cyc iv gx transceiver starter board yet. After not getting anything from that output ever I decided to take the clock, assign it to an output wire (also a conduit) so I can see what that is doing. It too does nothing (in the zip file the clock isnt set as a differential pair but I've checked the clock and its flipping along just fine).

At this point, I am convinced that there is some kind of disconnect between qsys and everything else in my system. I use a bdf which seems to be the unpopular method of setting up a top level design but thats what I have always done and I think its very easy to see what is going on (and I don't know SV yet). So I have qsys make a block which then gets connected in the top level bdf, so the signals should be getting to qsys. In generating the custom component I only use my logic .v file for synthesis, copy it over for simulation (I'm still not super clear what the difference between those 2 things is) however I noticed examples have a 2nd file which is some kind of interconnecty file so I am starting to wonder if that is somehow what I am missing (I am reffering the 2 files in the box on page 14 of Altera's "Making Qsys Components" pdf). Qsys populates the list of signals when analyzing the .v file, although it sets them all wrong and it needs to be changed. I do NOT have any parameters but I assume those are timing parameters. Lastly all the avalon interrconnect stuff is fine, so I'm really unsure of how I could be losing literally every signal in my design.