Altera_Forum
Honored Contributor
8 years agoQsys Avalon Streaming Sink in Component Editor
Hi,
I am struggling with the Component Editor in Qsys. I would like to use the SGDMA IP the produce a 64-bit Avalon stream from memory. This is done by 8 parallel streams of 8 bits (see screenshot). However, I am not able to produce the same waveform in my own component. The editor always drafts one input data of 8 bits (see screenshot). The data sink port is initialized with a 64-bit vector.
module avalon_interface (//inputs
clock,
resetn,
ctrl_write_data,
ctrl_read,
ctrl_write,
ctrl_address,
in_sink_valid,
in_sink_data,
in_sink_sop,
in_sink_eop,
weight_sink_valid,
weight_sink_data,
weight_sink_sop,
weight_sink_eop,
weight_data_empty,
out_source_ready,
//outputs
ctrl_read_data,
in_sink_ready,
weight_sink_ready,
out_source_valid,
out_source_data,
out_source_sop,
out_source_eop
);
input clock;
input resetn;
input ctrl_write_data;
input ctrl_read;
input ctrl_write;
input ctrl_address;
input in_sink_valid;
input in_sink_data;
input in_sink_sop;
input in_sink_eop;
input weight_sink_valid;
input weight_sink_data;
input weight_sink_sop;
input weight_sink_eop;
input weight_data_empty;
input out_source_ready;
output ctrl_read_data;
output in_sink_ready;
output weight_sink_ready;
output out_source_valid;
output out_source_data;
output out_source_sop;
output out_source_eop;
Do you have any suggestions what I have to change to get the same waveform as that of the SGMDA IP? Thank you very much, Jan