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Altera_Forum's avatar
Altera_Forum
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14 years ago

Qsys and multiple slave SPI

I am trying to move a design from SOPC to QSYS mainly to allow software to read which device in the FPGA is interrupting through PCIe.

I have one SPI master that has two slaves, that isn't moving over because QSYS isn't generating SSn as a vector. In Qsys the spi core is set to 2 slaves, but the QSYS system inspector shows the SSn as being 1 bit wide. When I look in the verilog generated for the SPI core is it two bits wide, but the verilog generated for the system is one bit wide.

Is this fixed in SP1, did I do something wrong, or do I tell software they are stuck with prioritized interrupts and all the reads?

Rob

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    This is a known bug and it has not been fixed yet. The SPI core itself is generated correctly but when it gets wired up to the top level it is only done for a single bit so for now the only workaround is to hack up the top level file manually to make sure the other bits get connected.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Well that sucks, but what it is what I suspected I would have to do. It does leave room for error if something changes.

    Thanks,

    Rob