Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Qsys and multiple slave SPI

I am trying to move a design from SOPC to QSYS mainly to allow software to read which device in the FPGA is interrupting through PCIe. I have one SPI master that has two slaves, that isn't mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

This is a known bug and it has not been fixed yet. The SPI core itself is generated correctly but when it gets wired up to the top level it is only done for a single bit so for now the only workaround is to hack up the top level file manually to make sure the other bits get connected.