Qsys and basic signals

Ok, so you now have the address, clken, signals etc. To write a word to the memory you need something along the lines of:

process(clk)

if (rising_edge(clk)) then

addr <= addr + 1;

clken <= '1';

chipselect <= '1';

write <= '1';

writedata <= X"1234";

byteenable <= "1111";

end if;

end process;

This will (assuming addr is initialised on a reset signal or similar) fill your memory with 0x1234 and increment the address every clock cycle. Obviously you can change the write data each clock cycle, or you can pause the write with setting "write <= '0'" when not ready.

Basically to write a word, setup the address, chipselect, clken, write, byteenable and writedata signals, and keep them there for a clock cycle (the same clock that you clock the memory with). To read a word you need address, chipselect, and clken and the data will appear on the following clock cycle on the readdata bus.