Qsys and basic signals

simonkbrown

Hello, Thank you for answer.

Exactly yes - i am want write few bytes to on chip memory via VHDL and avalon mm bus.

Now i am remove master template, export slave and have in entity next:

Use this for write or read - this input pins i am dont understand what.

Sorry , i am really want understand avalon bus working logic.

Thank you for answer.

entity hd_mem is

port (

clk_clk : in std_logic := '0'; -- clk.clk

onchip_mem_s1_address : in std_logic_vector(10 downto 0) := (others => '0'); -- onchip_mem_s1.address

onchip_mem_s1_clken : in std_logic := '0'; -- .clken

onchip_mem_s1_chipselect : in std_logic := '0'; -- .chipselect

onchip_mem_s1_write : in std_logic := '0'; -- .write

onchip_mem_s1_readdata : out std_logic_vector(15 downto 0); -- .readdata

onchip_mem_s1_writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata

onchip_mem_s1_byteenable : in std_logic_vector(1 downto 0) := (others => '0'); -- .byteenable

reset_reset_n : in std_logic := '0' -- reset.reset_n

);

end entity hd_mem;