Forum Discussion
Altera_Forum
Honored Contributor
12 years agoQSYS - Send data to all slaves at the same time
Hi,
I wonder if it is possible to somehow create a QSys design that has one master (in this case a time provider) that sends the timing information to all connected slaves at the same time (say clock edge). I think, I cannot use Avalon Master/Slave or AXI Master/Slave architectures because they only support dedicated slave addressing and qsys does not allow 2 or more slaves to share the same address. I tried to internally (-> inside QSys) connect cunduits of the components, but I'm only able to directly connect two components. My current workaraound is to connect all components via conduits that i route outside the QSys system and connect them in the top level bdf file. I would like to get rid of this top level routing if possible. Any ideas or recommendations? Regards, Maik2 Replies
- Altera_Forum
Honored Contributor
I'd suggest sending the timing signal using ST-source, You can copy/split this over multiple receiving ST-sinks
- Altera_Forum
Honored Contributor
With your hint in mind, I searched through the Qsys component library and found the Avalon-ST splitter component. That looks quite promising. Thank you!