Hello everyone, i have created a qsys-system with a state machine working as an avalon memory mapped master and a pio working as an avalon memory mapped slave. The Master uses 32bit for addresses and 16bit data. The slave uses a 2 bit address and 8bit data. The pio slave is connected to leds. Now the problem: If i use a base address for the slave like 00000000hex or 02000000hex than it seems to function as aspected but if i use a base address like 02000008hex nothing happen. If i try to set the base address to an address like 02000001, i get an error that the base address cannot be at 02000001 (02000000 or 02000008 are acceptable). Why can't i use base addresses like 02000008hex? thanks and regards, schlittk

You modify QSYS : manually change base addresses for your Qsys component. QSYS can do this semi-automatically (menu ...). Why not. Did you regenerate Qsys ? YES, I think Did you recompile the whole project. I had similar when my Qsys was NOT in the root directory of my project (Nios II recognize an old qsys). Did you regenerate the associated BSP in NIOS II SBT ? In order to update the system.h (where "#define PIO_LED_BASE (0x02000008)"). I think your problem is here In your software, how do you write to your PIO ? by IOWR...(0x02000000, data) or IOWR_...(PIO_LED_BASE, data) You can let Quartus decide for base addresses except for Flash memory that should be locked at address 0x0000. Easier.

Yes, i have regenerated QSYS and recompiled the quartus project. An old qsys can't be the error source because a change from working address 0x02000000 to working address 0x00000000 is not a problem. I don't use a NIOS. My system consist only of a state machine working as an avalon memory mapped master and a pio working as an avalon memory mapped slave. No more. For that reason there is no Software. The base address 0x02000008 was automatical generated by qsys but the components with lower addresses are removed for debug requirements. I plan to bring this components back to the design thats why i wanted to use this address. To use this address is not importend to me, more why i can't.

Does your state machine Avalon Master handle the 8 byte offset?

I'm not sure whether you mean that i change the address i write to from 0x02000000 to 0x02000008 then yes i handle the offset. An another abnormal bahavior i have seen is when i set the base address for the pio in qsys to 0x02000008 and in my state machine Avalon Master the write destination address to 0x02000010 or 0x02000011 it seems to work correctly.

Still looks to me that your state machine Avalon Master doesn't handle the offset 8 correctly. Maybe post the code?

Qsys - Base Address Problem | Altera Community

19 Replies

Altera_Forum
Honored Contributor
11 years ago
You really want the data widths to match, otherwise a 'bus width adapter' is added that will convert a single master access into multiple slave ones.
In many cases an adapted that just padded out the data bus would work fine - but that isn't what you get.
These adapters (and clock crossing bridges) are added 'by magic' and their presence isn't easy to determine.
Altera_Forum
Honored Contributor
11 years ago
So it has a 32 bit wide databus on the Avalon fabric. and then an offset of 8 isn't possible as the PIO has 4 - 32bit words address space. That may explain why setting the address to 0x02000010 in your Avalon master works.
I do not have a 16 bit Avalon MM Master at hand, and none seem to be available from the Qsys Library panel.
Maybe Qsys errs by allowing you to set the address to 0x020000008.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
You really want the data widths to match, otherwise a 'bus width adapter' is added that will convert a single master access into multiple slave ones.
In many cases an adapted that just padded out the data bus would work fine - but that isn't what you get.
These adapters (and clock crossing bridges) are added 'by magic' and their presence isn't easy to determine.
--- Quote End ---

I can't get the data widths to match. I want to use the sdram controller. When i look in qsys system inspector for the s1 signals i see that readdata and writedate uses 16 bit. Thats why i use 16 bit data bus for the master. The pio i use used only 8bit for writedata and readdata. Both of them are created by qsys.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
So it has a 32 bit wide databus on the Avalon fabric. and then an offset of 8 isn't possible as the PIO has 4 - 32bit words address space. That may explain why setting the address to 0x02000010 in your Avalon master works.
I do not have a 16 bit Avalon MM Master at hand, and none seem to be available from the Qsys Library panel.
Maybe Qsys errs by allowing you to set the address to 0x020000008.
--- Quote End ---

How can i see that the altera_avalon_pio uses 32bit databus? If i look in qsys system inspector for the s1 signals of the pio i see that readdata and writedate uses only 8 bit.
Altera_Forum
Honored Contributor
11 years ago
If you doubleclick on the PIO in the System Contents and then check the show signals in the Block Diagram you will see that the databus width is 32 and cannot be altered.
Funny, I see 32 bits in the system inspector.
What version of Qsys/Quartus II are you using? In fact that should have been the first question to ask ...
I am using Qsys 13.1 Build 173
Altera_Forum
Honored Contributor
11 years ago
I use a little bit older version ;-) quartus II 10.1 build 153.
Altera_Forum
Honored Contributor
11 years ago
Then you shall have no pie :)
Any particular reason to stick to 10.1?
Altera_Forum
Honored Contributor
11 years ago
No not really. I will try the same with a newer version.
Altera_Forum
Honored Contributor
11 years ago
Now I have tried a newer version. In 13.1 the pio uses 32 bit and the problem with the base address are resolved.

Thank you.

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Qsys - Base Address Problem

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