--- Quote Start ---
You really want the data widths to match, otherwise a 'bus width adapter' is added that will convert a single master access into multiple slave ones.
In many cases an adapted that just padded out the data bus would work fine - but that isn't what you get.
These adapters (and clock crossing bridges) are added 'by magic' and their presence isn't easy to determine.
--- Quote End ---
I can't get the data widths to match. I want to use the sdram controller. When i look in qsys system inspector for the s1 signals i see that readdata and writedate uses 16 bit. Thats why i use 16 bit data bus for the master. The pio i use used only 8bit for writedata and readdata. Both of them are created by qsys.
Honored Contributor
