QIP File doesn't include the submodules after adding in a certain conneciton

I was finally able to figure it out. What seemed to happen was, I was using an APB translator to interface with the AXI slave port on the HPS. I didn't select "USE_MADDR31" (or some parameter like that). My assumption is that it made a 31bit APB connection opposed to the desired 32 bit. I think that Qsys tried to do a interconnect block and just crapped out. However, it did not give any errors or warnings about it. I just happened to notice in the interconnect flow chart that there were two width interconnects. That didn't seem correct so I played around until I found that parameter. Once I set that, it seemed to resolve the issue.