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What Sanmao is saying is that it is not considered good practice to use clock as data. If you connect a clock signal to the
data input (and not the clock) of a register, you are using clock as data. This is why Quartus might give you a warning. You said Quartus didn't let you, but we assume it was just a warning because it does let you.
As every good practice, there are times when it might make sense to ignore it. But in most cases you should not.
As Pletz asked, try to repost your BDF complete and at higher resolution, otherwise we can't see what you are trying to do.
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The reason for putting clock into logic in this case was to invert the signal in a NOT gate so I could use Clock and NotClock to more reliably control the timing of the circuit, knowing that the delay of the signal was sub-5us for the circuit before and using a NotClock after a Clock was used for the DFF gating for delay and one-shot purposes.
I am sorry about the post being poor resolution. The original I provided to the forum was an 184KB .gif file, which was decimated to an 11.9KB jpg when I tried again today to attach it. It is now OBE (overcome by events) as the base problem, as described above, was a bug in the .bdf editor that allows one to drop a NOT gate over a wire, merging the terminals of the NOT gate to the wire, then allowing deletion of the connection between NOT gate input and output, whilst keeping the wire declaration for either side of the NOT gate ***IDENTICAL***. This is huge, and has impacted several of my .bdf function blocks as I am used to schematic entry programs that properly handle this sequence of operations.
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