Honored Contributor
Honored Contributor"I do not see the need why you would need a derived clock or why you would be obliged to steer logic directly from a clock signal."
Hi Sanmao, Now I am really puzzled... The purposes of this circuit are: 1. Generate a series of time-sequenced pulses to control external analog and RF circuit operations. The sequencing of these operations enables the operation of our circuit as a whole. 2. Generate synchronous and asynchronous serial interfaces for several different devices. 3. Translate to/from the asynchronous serial interface for communications with the synchronous serial interfaces. For these purposes, operation of the CPLD as a state machine is not adequate. I must use a clock signal from somewhere to generate the sequencing and timing required. I understand there is likely a better way than I have chosen, and am very much open to learn what this might be. One other request, as I am originally a C/C++ and hardware type, who is an extreme novice at VHDL and its kin: Is there a simple way to put your last reply into a .bdf form, or implement it using the Assignment IDE?
