QII to QIISP2 Migration, Warning: Entity "xxx" contains only dangling pins

Hi Roger,

--- Quote Start ---

The MAX II series have no PLL's so our only choice is to use an external clock to drive at least some logic in the circuit...

--- Quote End ---

Even if no PLLs are available you should not drive logic by clock signals to make derived clocks. In this case the best thing to do is to use the clock available to clock your registers and flip-flops.

In case you need something like a "clock" at a lower speed, what you actually have to do is to use an enable signal or so. An example of this is as follows:

 
always @(posedge clock)
  if (reset)
    ... blah blah blah ...
  else begin
    if (enable) begin
       ... do here the things that you want to do under certain conditions
       ... or at a lower speed.
    end
  end

the enable signal can be generated from other always processes.

I do not see the need why you would need a derived clock or why you would be obliged to steer logic directly from a clock signal.

Hope this helps...