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@roger,
It is in general no good design practice to use external clock signals for other applications than clocking registers and flip-flops (or as inputs to PLLs).
So the compiler is hinting you not to do this. Switching to other versions of the software is not a solution to the basic problem.
Hope this helps...
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Thank you for the input, and it applies well for FPGA's (I have used the Cyclone III this way) that have PLL's. The MAX II series have no PLL's so our only choice is to use an external clock to drive at least some logic in the circuit... Further, QII has a bad habit of not following the documentation and optimising out buffers inserted in code to limit fanout for timing control purposes. As such you have further highlighted a "basic problem" that the compiler is not well versed on the capabilities of the device for which it is compiling. You are correct, however, about switching to the newer version of QII, which did not help.
After much effort, I have determined that the strange failure to compile was fixed simply by attempting to re-compile the exact same code. For some reason, the compiler did not properly place the results of its own first try enumeration and pin assignments where it could use them so was unable to complete the compilation (looks like a bug to me). It is also frustrating that the documentation with Quartus II or online nowhere describes the reason or meaning of the dangling pins error.
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