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17 years agoQII 8.1: Incremental Compilation and Signal Tap
Hi all I'm using Quartus II ver 8.1.
My project has 1 top, 2 partitions (containing ASI IP blocks) and 1 Nios Project Partition. Told that the problem is now I'm in debug phase of the project and I cannot use the signal tap! The problem arise because all the Signal Tap I've tried to generate seems to put the CLK at ground each time (I've used always clk that are output of PLL). It doesn't depend if I instantiate one ore more signal tap instance, but the problem persists also if I change all the data and the clk (in order to see different things). The message is that after the syntesis the CLK of the signal tap is put at GND!. At first I thought was something about STP of Quartus 8.1 because the project arose in QII 8.0 and I've used STP, but after the NIOS guy started to use all the features of Nios 8.1 I've had to switch the project in QII. But it is not this case because I've tried to do a simple project in order to test the STP and it works. I can tell you that all time I'm trying to monitor the signals in the TOP partitions and I've used always the "Signal Tap: Presynthesis" signal in my stp. I'm sure that the block are almost working because I've the out signal of the block that almost is the one I want and I've tried also to put on pin to phisically see the CLK and leave it there also in other compilations. What can I try? Is changed something in the last QII signal tap? (I Instantiate it creting it from quartus, not with the megawizard way).