PWM generator

I suggest that you consider the use of ieee.numeric_std and VHDL 2008, at least the construts in VHDL 2008 as supported by Quartus at this time. (Altera, we are still waiting for full support of VHDL 2008!)

I put together a quick snippet of code for what I think that you want to do. Note that I use a record type to clarify the PWM signals. There are effectively three states: one during the duty cycle on time, one during the duty cycle off time, and one to reset the counter (which really isn't a state, just a resetting of the pwm counter.) Best, James

architecture RLT of PWMgenerator is
type pwmType is record
    drive : std_logic;
    dutyCycle : integer range 0 to 2**24;
    Period    : integer range 0 to 2**24;
end record;
signal pwm : pwmType;
begin
pwm.Period    <= someValue;  -- (Would come from port I/O)
pwm.dutyCycle <= someIncomingValue; -- (Would come form port I/O)
process(all)
variable counter : integer;
begin
if HRST then
    pwm.drive <= '0';
elsif rising_edge(MCLK) then
    if counter < pwm.dutyCycle then
        counter := counter + 1;
        pwm.drive <= '1';
    elsif counter < pwm.Period then
        counter := counter + 1;
        pwm.drive <= '0';
    else
        counter := 0;
        pwm.drive <= '0';
    end if;
end if;
end process;