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Altera_Forum
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17 years ago

PUF in an FPGA

I am making a circuit that runs a pulse through a large amount of multiplexers. I want to create a race condition arbitrated by a RS flip-flop (Latch). This basic design is then replicated for as man...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

See the recent topic "simple" delay chain mystery for a detailed discussion how to place logic cells intentionally by using a keep synthesis attribute. You should also get familiar with the Quartus Netlist Viewer tools to check the achieved results.