PUF in an FPGA

The said paper was among the literature I consulted to understand the topic. I didn't yet consider the possible problems of ring oscillator realization with FPGA. These constructs are beyond my regular horizon of synchronous FPGA designs. I guess, that the general situation could be similar to the multiplexer case. I didn't mean, that they would be completely unrealizable. Your previous results are probably due to ignoring the usual behaviour of FPGA compilers. To get a logic structure exactly as you designed it, you have to switch off respectively block all optimization steps of the compiler. You should be able to realize at least some elements of puf behaviour then.