PUF in an FPGA

To be honest, I don't yet see what's the mechanism to create independent random states in the said way. Can you give a one bit design example that also allows to analyze why Quartus doesn't understand your intentions.

P.S.: I understand, that the intention is to generate an unique device signature. I think this may be difficult based on FPGA delay variations.

P.P.S: A classical puf multiplexer circuit as presented by Daihyun Lim would be completely removed during compilation without keep attributes, see the recent discussion in this forum. Furthermore, an always zero output simply indicates, that the delay variation is smaller than the setup time of the latch used as arbiter. Finally I fear, that the systematic delay variations caused by logic cell and routing topology may be considerably higher than the contribution of random, chip specific variation. Thus the method would fail. Designing an almost symmetric topology would require means beyond the capabilities of Quartus user interface. A more symmetric arbiter (at least a systematic correction for the setup time) should be used anyway.